`timescale 1ns/1ps
module cpu_spoc_tb(
);
  reg     clk;
  reg     rst;
    
  initial begin
    clk = 0;
    forever 
    #10 
    clk = ~clk;
  end
      
  initial begin
    rst = 1;
    #150 
    rst= 0;
    #1850 
    $finish;
  end
       
  cpu_spoc cpu_sopc0(
		.clk(clk),
		.rst(rst)	
	);

endmodule